Method of fabricating a high-voltage metal-gate CMOS device

ABSTRACT

A method of fabricating a high-voltage metal-gate CMOS device is disclosed. First, a semiconductor substrate of a first conductivity type having a well region of a second conductivity type is provided. Next, a barrier layer is formed and patterned to form openings for prospective source/drain regions. Then, through the openings, low concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the well region and the semiconductor substrate, respectively. After performing a first thermal treatment, lightly doped source/drain regions of the first conductivity type and the second conductivity type are formed respectively, wherein an oxide layer is also formed within the openings. A sidewall spacer is formed on the sidewalls of the openings. Then, through the openings, high concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the lightly doped source/drain regions of the first conductivity type and the second conductivity type, respectively. After removing the sidewall spacer performing a second thermal treatment, heavily doped source/drain regions of the first conductivity type and the second conductivity type are formed respectively. Further, the barrier layer is patterned to expose areas of the semiconductor substrate and the well region for the prospective gate electrode. Finally, a gate oxide layer and a metal gate electrode are formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to the fabrication of integratedcircuit (IC) devices, and more particularly to a method of fabricating ahigh-voltage metal-gate CMOS device having heavily doped source anddrain regions that are precisely formed within the lightly doped sourceand drain regions, so as to guarantee the uniformity of devicecharacteristics.

2. Description of the Prior Art

Under current technology of fabricating high-voltage CMOS devices, apolysilicon layer is normally used as the gate electrode of a CMOSdevice. The polysilicon gate electrode configuration, however, requiresa relatively long manufacturing cycle time. Thus the manufacturing costis raised by such a long cycle time. Furthermore, due to their inherentcharacteristics, CMOS devices with polysilicon gate electrodes usuallyencounter a latch-up problem which is fatal to the operation of thedevices.

By replacing the polysilicon gate electrode with a metal gate electrode,the cycle time of manufacturing a high-voltage CMOS device can bereduced and the latch-up problem can be prevented. However, theconventional process for fabricating a high-voltage metal-gate CMOSdevice suffers from poor dimensional alignment and symmetry for thefabricated source/drain regions that are prerequisites for theuniformity of the electrical characteristics for these CMOS devicesfabricated. These poor alignment and symmetry characteristics found inthe conventional fabrication processes are inherent to the nature of thefabrication process steps employed. Poor alignment in the source anddrain regions of the CMOS device result in variations of the electricalcharacteristics for CMOS devices produced in different productionbatches, as the fabrication process conditions may vary for thealignments involved in the process steps.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a processfor fabricating high-voltage CMOS devices having a metal gate electrodeto reduce the manufacturing cycle time and prevent latch-up.

It is yet another object of the present invention to provide a processfor fabricating high-voltage CMOS devices with their heavily dopedsource and drain regions precisely formed within the lightly dopedsource and drain regions in a self-aligned manner, ensuring uniformityof device characteristics.

The present invention achieves the above-identified objects by providinga method of fabricating a high-voltage metal-gate CMOS device. First, asemiconductor substrate of a first conductivity type having a wellregion of a second conductivity type is provided. Next, a barrier layeris formed overlying the semiconductor substrate and the well region. Thebarrier layer is etched to form openings exposing portions of thesemiconductor substrate and the well region for prospective source/drainregions. Then, through the openings, low concentrations of impurities ofthe first conductivity type and the second conductivity type areimplanted into the well region and the semiconductor substrate,respectively. After performing a first thermal treatment to drive-in thelow concentration of impurities, lightly doped source/drain regions ofthe first conductivity type and lightly doped source/drain regions ofthe second conductivity type are formed respectively, wherein an oxidelayer is also formed within the openings by the first thermal treatment.A sidewall spacer is formed on the sidewalls of the openings. Then,through the openings, high concentrations of impurities of the firstconductivity type and the second conductivity type are implanted intothe lightly doped source/drain regions of the first conductivity typeand the lightly doped source/drain regions of the second conductivitytype, respectively. After removing the sidewall spacer and performing asecond thermal treatment to drive-in the high concentration ofimpurities, heavily doped source/drain regions of the first conductivitytype and heavily doped source/drain regions of the second conductivitytype are formed respectively, wherein the thickness of the oxide layeris increased. Further, the barrier layer is patterned to expose areas ofthe semiconductor substrate and the well region for the prospective gateelectrode. A gate oxide layer is formed on the areas for the prospectivegate electrode. The oxide layer is then etched to form contact openings.Finally, a metal gate electrode is formed on the gate oxide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome apparent by way of the following detailed description of thepreferred but non-limiting embodiment. The description is made withreference to the accompanying drawings, wherein:

FIGS. 1a to 1e, respectively, show schematically cross-sectional viewsof the high-voltage metal-gate CMOS devices fabricated in the process inaccordance with a preferred embodiment of the present invention asdepicted in selected process stages, wherein the left hand side shows anNMOS transistor and the right hand side shows a PMOS transistor.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the process in accordance with the presentinvention for fabricating a high-voltage metal-gate CMOS device withprecision alignment and dimensional symmetry is described below byreferring to FIGS. 1a to 1e. As persons skilled in the art may wellappreciate, the process of the present invention may be applicable to asemiconductor substrate of a first conductivity type with a well regionof a second conductivity type (e.g. a P-type substrate with an N-typewell region or an N-type substrate with a P-type well region), althoughit is an N-type substrate 1 employed for the description. When theinventive process is described, the steps for fabricating both the NMOSand PMOS transistors of the CMOS device configuration are simultaneouslyexemplified. Since the NMOS and PMOS transistors that constitute thecomplementary pair are fabricated on the same substrate, if an N-typesubstrate 1 is employed, as in the case of the exemplified embodimentdepicted in the drawings, then for the NMOS transistor, a P-well 2 willhave to be prepared by a conventional implanting process. On the otherhand, no corresponding N-well is required for the PMOS transistor.

Stage 1

As is shown in FIG. 1a, a barrier layer 10 is formed on thesemiconductor substrate 1 of the first conductivity type with a wellregion 2 of the second conductivity type. For example, an oxide layer 10is formed by thermal oxidation on an N-type substrate 1 with a P-typewell region 2. The barrier layer 10 is patterned by conventionallithography and etching processes to form openings 12 and 14 whichexpose portions of the semiconductor substrate 1 and the well region 2for prospective source/drain regions. Then, through the openings 12 and14 respectively, low concentrations of impurities of the firstconductivity type are implanted into the position 16 of the well region2 and impurities of the second conductivity type are implanted into theposition 18 of the semiconductor substrate 1. For example, N-typeimpurities such as phosphoric ions are first implanted into the P-typewell region 2. Then, P-type impurities such as boron ions are implantedinto the N-type substrate 1.

Stage 2

Next, referring to FIG. 2b, a first thermal treatment is performed todrive-in the implanted low concentration of impurities. Therefore, N⁻lightly doped source/drain regions 16 and P⁻ lightly doped source/drainregions 18 are formed in the P-type well region 2 and the N-typesubstrate 1, respectively. Meanwhile, an oxide layer 19 is also formedwithin the openings 12 and 14. Subsequently, a sidewall spacer 21 isformed on the sidewalls of the openings 12 and 14. For example, an oxidelayer is first formed by chemical vapor deposition (CVD). That oxidelayer is then etched back by reactive ion etching (RIE) to form thesidewall spacer 21. After that, through the openings 12 and 14 havingthe sidewall spacer 21, high concentrations of impurities of the firstconductivity type and the second conductivity type are implanted intothe lightly doped source/drain regions 16 and 18 respectively. Forexample, N-type impurities such as arsenic ions are first implanted intothe position 22 of the N⁻ lightly doped source/drain regions 16. Then,P-type impurities such as boron ions are implanted into the position 24of the P⁻ lightly doped source/drain regions 18.

Stage 3

Then, as is shown in FIG. 1c, the sidewall spacer 21 is removed by aconventional etching process. A second thermal treatment is performed todrive-in the implanted high concentration of impurities. Therefore, N⁺heavily doped source/drain regions 22 and P⁺ heavily doped source/drainregions 24 are formed in the N⁻ lightly doped source/drain regions 16and the P⁻ lightly doped source/drain regions 18, respectively.Meanwhile, the thickness of the oxide layer 19 is increased due to thesecond thermal treatment.

Stage 4

Referring next to FIG. 1d, the barrier layer 10 is patterned bylithography and etching processes to form openings 25 exposing areas ofthe semiconductor substrate 1 and the well region 2 for the prospectivegate electrode. Next, a gate oxide layer 27 with a thickness of between200 Å to 1000 Å is formed within the openings 25 by thermal oxidation orCVD. Again, the thickness of the oxide layer 19 is increased.

Stage 5

As is shown in FIG. 1e, the oxide layer 19 is patterned by lithographyand etching processes to form contact openings 29 exposing the heavilydoped source/drain regions 22 and 24. A metal layer, such as an aluminumlayer, is sputtered on the surface of substrate. The metal layer is thenpatterned by etching to form a metal gate electrode 31a and metal lines31b, wherein the metal gate electrode 31a is over the gate oxide layer27. The metal lines 31b are connected to the heavily doped source/drainregions 22 and 24 through the contact openings 29. This generallyconcludes the fabrication of the high-voltage metal-gate CMOS devicecomprising the NMOS and PMOS transistor pair on an N-type substrate witha P-type well region.

As is appreciable after reading the above description of the fabricationprocess in accordance with the exemplified preferred embodiment, personsskilled in the art may acknowledge the advantages inherent to theprocess of metal-gate CMOS device fabrication as disclosed by thepresent invention. Since the implantation of the lightly dopedsource/drain regions 16 and 18 are guided by the openings 12 and 14formed on the barrier layer 10, and the implantation of the heavilydoped source/drain regions 22 and 24 are guided by the sidewall spacer21 formed on the sidewalls of the openings 12 and 14, the precisealignment of the heavily doped source/drain regions 22 and 24 within thelightly doped source/drain regions 16 and 18 can be achieved. Thisresults in the improvement of the uniformity of the electricalcharacteristics of the CMOS device. Moreover, the manufacturing cycletime can be reduced since the metal gate electrode 31a and the metallines 31b are formed in a single patterning step.

The above-described preferred embodiment of the present invention isutilized only for the purpose of the description of the presentinvention. Persons skilled in this art can appreciate the fact thatother similar arrangements can be devised from the embodiment disclosedabove without departing from the spirit of the present invention, whichis recited in the following claims.

What is claimed is:
 1. A method of fabricating a high-voltage metal-gateCMOS device, comprising the steps of:providing a semiconductor substrateof a first conductivity type having a well region of a secondconductivity type; forming a barrier layer overlying said semiconductorsubstrate and said well region, and etching said barrier layer to formopenings exposing portions of said semiconductor substrate and said wellregion for prospective source/drain regions; selectively implanting,through said openings, low concentrations of impurities of the firstconductivity type into said well region of the second conductivity typeand impurities of the second conductivity type into said semiconductorsubstrate of the first conductivity type; performing a first thermaltreatment to drive-in said low concentrations of impurities to formlightly doped source/drain regions of the first conductivity type andlightly doped source/drain regions of the second conductivity typerespectively, wherein an oxide layer is also formed within said openingsby said first thermal treatment; forming a sidewall spacer on thesidewalls of said openings; selectively implanting, through saidopenings, high concentrations of impurities of the first conductivitytype into said lightly doped source/drain regions of the firstconductivity type and impurities of the second conductivity type intosaid lightly doped source/drain regions of the second conductivity type;removing said sidewall spacer; performing a second thermal treatment todrive-in said high concentrations of impurities to form heavily dopedsource/drain regions of the first conductivity type and heavily dopedsource/drain regions of the second conductivity type respectively,wherein the thickness of said oxide layer is increased; patterning saidbarrier layer to expose areas of said semiconductor substrate and saidwell region for the prospective gate electrode; forming a gate oxidelayer on said areas for the prospective gate electrode; etching saidoxide layer to form contact openings; and forming a metal gate electrodeon said gate oxide layer and forming metal lines connecting to saidsource/drain regions through said contact openings.
 2. The method ofclaim 1, wherein said first conductivity type is N type and said secondconductivity type is P type.
 3. The method of claim 1, wherein saidfirst conductivity type is P type and said second conductivity type is Ntype.
 4. The method of claim 1, wherein said barrier layer is a silicondioxide layer.
 5. The method of claim 1, wherein said sidewall spacer isa silicon nitride layer.